Resistor-string digital to analog converters (DAC's) are the most basic form of DAC, typically suitable for mid-accuracy applications (up to 10 bits). They are of special importance in processes having no high-quality capacitors available. Among their advantages are monotonicity (the value rises and never falls; or it falls and never rises), simple design and exclusively passive circuitry.
The drawback of a “straightforward” resistor ladder is the number of elements. I.e., the number of resistors and switches equals 2N in order to achieve N bits of accuracy. A large number of switches are particularly disturbing. Apart from consuming area, they load the ladder with parasitic capacitance and complicate the control logic.
Patents related to improving the speed/power of dual ladder DAC's in various ways are known in the art. For example, U.S. Pat. No. 5,703,588, Digital To Analog Converter With Dual Resistor String, by Rivoir, et al, discloses a dual resistor string digital-to-analog converter, wherein current biasing is used to isolate a first resistor string from a second resistor string. The first resistor string consists of multiple first resistors and a first switch network responsive to the most significant bits (MSB's) selectively couples the second resistor string in parallel to any one first resistor within the first resistor string. To prevent the second resistor string from drawing current from the first resistor string, a current source feeds a bias current into the second resistor string and a current drain draws the bias current from the second resistor string. The bias current is adjusted such that the voltage drop across the whole of the second resistor string is equal to the voltage drop across any one first resistor within the first resistor string. Use of a current source and current drain allows one to freely adjust the number of MSB's, least significant bits (LSB's) and both first and second resistor magnitudes to obtain optimum performance, without concern for any adverse nonlinearity effects.
Also, U.S. Pat. No. 5,252,975, Digital To Analog Converter Having Resistor Networks, by Yuasa, et al, teaches a D/A converter, including a first resistor network, said network including K resistors, where K is an integer, and a second resistor network including L resistors connected in series, where L is an integer. The sum of resistances of the L resistors is approximately equal to the resistance of each of the K resistors. The D/A converter further includes a first switching part, coupled to the K resistors, for selecting (K−1) resistors among the K resistors in accordance with a digital input signal and for forming a series circuit including the (K−1) resistors and the second resistor network connected in series, first and second voltages being applied to respective ends of the series circuit. Furthermore, the D/A converter includes a second switching part, coupled to the second series circuit, for connecting one of the L resistors to an output terminal of the D/A converter.
The prior art of DAC ladder design includes the following references:    [1] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995    [2] M. J. M. Pelgrom, “A 10-bit 50-MHz CMOS D/A Converter with 75-Ω Buffer,” IEEE Journal of Solid State Circuits, vol. 25, no. 6, pp. 1347-1352, December 1990.]    [3] F. Maloberti, R. Revoir and G. Torelli, “Power Consumption Optimization of 8-bit, 2 MHz Storage Scaling Subranging CMOS 0.5 μm DAC in Process IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS '96), Rodos, Greece, October 1996, pp. 1162-1165.    [4] L. E. Boylston, J. K. Brown and R. Giger, “Enhancing Performance in Interpolating Resistor String DAC's,” in Process IEEE 45th Midwest Symposium on Circuits and Systems, (MWSCAS '02), VOL. 2, August 2002, pp. 541-544.
The requirement for 2N elements can be relaxed through interpolating the voltages of the coarse most significant bit (MSB) ladder by means of the second fine, or least significant bit (LSB) ladder cite Razavi [1], Pelgrom [2] and Maloberti, et al [3]. If the coarse ladder provides Nc levels and the fine ladder provides Nf levels, the overall complexity is reduced to 2Nc+2Nf.
Using a secondary ladder degrades the DAC differential non-linearity (DNL), due to the finite ohmic load on the primary ladder. Static current flow through the secondary ladder causes a voltage drop on the inter-ladder switches, increasing the DNL even further. The errors are introduced at the fine ladder end points. For a DAC, DNL error is the difference between the ideal and the measured output value between successive DAC codes. An ideal DAC would have analog output values exactly one code apart (DNL=0). A DNL specification of greater than or equal to 1 LSB guarantees monotonicity.
Integral non-linearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-fit straight line or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. “Relative accuracy” is a term often used to refer to INL.
Several techniques for isolating the fine ladder from the coarse ladder by means of active buffers are presented in Boylston [4]. The drawback of this approach is the requirement for two large common mode buffers, with offsets matched up to the required DAC accuracy over the whole output range. Bandwidth requirement on the buffers contributes to overall power consumption.
Compensating for the secondary ladder loading effects provides an alternative to isolation by active circuitry. While completely passive compensation is possible, it severely degrades the dynamic performance. This is reviewed below.
Pelgrom [2] suggested another passive compensation scheme, which does not deteriorate the performance at the expense of a great increase in switch matrix complexity, with a return to 2N elements.
Maloberti, et al, [3] proposed compensating the load by forcing a constant current through the fine ladder. Only DAC active circuitry is involved, posing no bandwidth requirements. The power penalty therefore is modest. The switch matrix complexity is maintained at 2Nc+2Nf.
It would therefore be advantageous to provide a DAC that which addresses the issue of output resistance and parasitic capacitance by employing active circuitry current biasing of the LSB ladder.